1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device formed on an SOI (Silicon On Insulator) substrate and a method for manufacturing the same.
2. Description of the Related Art
FIGS. 1A and 1B show a conventional transistor on an SOI substrate (hereinafter, referred to as an SOI transistor) disclosed in Japanese Laid Open Patent Application (JP-P-Heisei 4-34980). FIG. 1A is a plan view of a structure of the conventional SOI transistor, and FIG. 1B is a cross sectional view along a dotted line X-X′ in FIG. 1A.
In the conventional SOI transistor, an SOI substrate has a silicon substrate 101, an insulating film 102 on the silicon substrate 101, and a silicon layer 103 (hereinafter, referred to as an SOI layer) on the insulating film 102. An active region is formed in the SOI layer 103, which includes a channel region 108, a source region 109 and a drain region 110. A gate electrode 105 is formed on the SOI layer 103 through a gate insulating film 104. An isolation insulating film 106 is formed on the SOI layer 103 around the active region. A well region 111 is formed under the isolation insulating film 106, into which impurity with the same conductivity type as in the channel region 108 is introduced. A body contact 107 is formed on a predetermined area of the well region 111 to penetrate the isolation insulating film 106. Contact holes 113 are formed in the interlayer insulating film 112 to reach the source and drain regions 109 and 110. Wiring layers 114 are formed to fill the contact holes 113. A wiring layer 115 is formed on the body contact 107 to electrically connect to the well region 111. This structure is characterized in that excess carriers in the channel region 108 can escape out of the SOI transistor through the well region 111, resulting in suppression of the floating body effects. Such a path through which excess carriers can escape from the channel region 108 is referred to as a “carrier path”, hereinafter.
A method of forming the isolation insulating film 106 is not disclosed in the JP-P-Heisei 4-34980. The isolation insulating film 106 may be formed by using a conventional method which have been generally adopted in a FET (Field Effect) transistor on a bulk substrate, as shown in FIGS. 2A to 2C. First, impurity is introduced into the SOI layer 103 (FIG. 2A). Next, the isolation insulating film 106 is formed on the SOI layer 103 through a thermal oxidation process or a CVD (Chemical Vapor Deposition) process (FIG. 2B). After that, a part of the isolation insulating film 106 is etched through a wet etching process to form the structure shown in FIG. 2C. The active region is to be formed under the region where the isolation insulating film 106 is removed. The carrier path is formed under the remaining isolation insulating film 106. In this case, therefore, it is impossible to introduce impurity into the carrier path with higher density than in the channel region.
FIGS. 3A to 3C show another method of forming the isolation insulating film 106 in FIG. 1B. A mask pattern such as a photo resist or a SiO2 film is formed on a predetermined area of the SOI layer 103, and then impurity is introduced into the SOI layer 103 (FIG. 3A). After the mask pattern is removed, the isolation insulating film 106 is formed on the SOI layer 103 (FIG. 3B). Next, a part of the isolation insulating film 106 is etched (FIG. 3C). In this case, an edge of the active region deviates from an edge of the carrier path as shown in FIG. 3C, i.e., the edge of the active region can not be located to self-align with the edge of the carrier path.
FIG. 4 is a cross sectional view showing a structure of another conventional SOI transistor disclosed in IEEE, Electron Device Letter, Vol. 18, pp. 102-104. In the conventional SOI transistor, an SOI substrate has a silicon substrate 130, an insulating film 121 on the silicon substrate 130, and an SOI layer 122 on the insulating film 121. An active region is formed in the SOI layer 122, which includes a source region 124 and a drain region 123. A gate electrode 125 is formed on the SOI layer 122 through a gate insulating film 126. An isolation insulating film 129 (hereinafter, referred to as a LOCOS region) is formed adjacent to the active region by a LOCOS (Local Oxidation of Silicon) method. A carrier path 127 is formed in a residue semiconductor layer under the LOCOS region 129. A body contact region 128 is connected to the carrier path 127. Excess carriers can escape out of the SOI transistor through the carrier path 127, resulting in suppression of the floating body effects.
Other conventional SOI transistors similar to the transistor shown in FIG. 4 are disclosed in the Symposium on VLSI Technology 1996, pp. 92-93, and Japanese Laid Open Patent Application (JP-P2000-294794A). In the other conventional transistor disclosed in JP-P2000-204794A, a full isolating trench is also provided next to the active region to reach the insulating film 121. In these conventional transistors mentioned above, as shown in FIG. 4, the carrier path 127 is formed under the LOCOS region 129, i.e. in the residue semiconductor layer. Therefore, thickness of the SOI layer 122 around the carrier path 127 becomes thinner than that in the active region.
FIG. 5 is a cross sectional view showing a structure of still another conventional SOI transistor disclosed in the Symposium on VLSI Technology 2000, pp. 154-155. In the conventional SOI transistor, an SOI substrate has a silicon substrate 130, an insulating film 121 on the silicon substrate 130, and an SOI layer 122 on the insulating film 121. An active region is formed in the SOI layer 122, which includes a source region 124 and a drain region 123. A gate electrode 125 is formed on the SOI layer 122 through a gate insulating film 126. Isolating trenches 131 and 132 exist in the SOI layer 122 around the active region, which are formed through an STI (Shallow Trench Isolation) process. The isolating trench 131 adjacent to the active region (hereinafter, referred to as a partial STI) does not reach the insulating film 121. A carrier path 127 is formed in a residue semiconductor layer under the partial STI 131. A body contact region 128 is connected to the carrier path 127. Excess carriers can escape out of the SOI transistor through the carrier path 127, resulting in suppression of the floating body effects.
Another conventional SOI transistor similar to the transistor shown in FIG. 5 is disclosed in Japanese Laid Open Patent Application (JP-P2002-217420A). In these conventional transistors mentioned above, as shown in FIG. 5, the carrier path 127 is formed under the partial STI 131, i.e. in the residue semiconductor layer. Therefore, thickness of the SOI layer 122 around the carrier path 127 becomes thinner than that in the active region.
When an SOI transistor such as a full-depletion SOI MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is designed to have a very thin SOI layer (typically 10 to 50 nm thickness), a carrier path in the SOI transistor also becomes very thin and hence resistivity of the carrier path increases. Therefore, it is necessary to increase impurity density in the carrier path more than that in the channel region of the SOI transistor. Also, it is preferable to locate the edge of the carrier path self-aligned with the edge of the active region of the SOI transistor. Moreover, when the carrier path is formed under a LOCOS region or a partial STI as in FIGS. 4 and 5, the carrier path becomes further thinner than the SOI layer. Such a carrier path is insufficient for avoiding the floating body effects. It is also preferable to make the carrier path applicable to an SOI transistor having an extremely thin SOI layer such as a full-depletion SOI MOSFET.
Also, when impurity density in the well region becomes too high in the conventional SOI transistor shown in FIGS. 1A and 1B, the strength of electric field between the source/drain region and the well region increases and hence leak current increases. Also, if the impurity density in the well region becomes high, a parasitic capacitance between the source/drain region and the well region increases, resulting in deterioration of operation speed of the SOI transistor. It is preferable to reduce the resistivity of the carrier path as possible with the leak current and the parasitic capacitance between the source/drain region and the well region being kept low.
Also, with regard to the processes shown in FIGS. 2C and 3C, when the isolation insulating film 106 is processed by a wet etching, the etching proceeds isotropically and hence the edge of the isolating insulating film 106 does not become steep. Also, the isolating insulating film 106 is etched horizontally due to the isotropic etching, which causes reduction of the area of the isolating insulating film 106. On the other hand, when the isolating insulating film 106 is processed by a dry etching, the surface of the SOI layer 103 where the active region is to be formed is exposed to plasmas used in the dry etching, which causes various defects. Moreover, there is a possibility that the SOI layer 103 is etched, because an etching selection rate of SiO2 to silicon is lower in the dry etching than in the wet etching. A device isolation method is desired with which the edge of the isolation insulating film is formed to be steep and the SOI layer where the active region is to be formed is not etched during the device isolation process.
Also, in the conventional SOI transistor shown in FIGS. 1A and 1B, the surface of the isolation insulating film 106 is located upper than the surface of the SOI layer 103 where the active region is to be formed, as shown in FIGS. 2C and 3C. Therefore, deposition of material of the gate electrode 105 over the SOI substrate results in a concavo-convex surface of the material layer. If the surface of the material layer is not flat when forming the gate electrode 105, the resist pattern and hence the formed gate electrode 105 would be deformed. Also, if the top and bottom surfaces of the material layer are not flat when forming the gate electrode 105 through an etching process such as an RIE (Reactive Ion Etching), the etching of a part of the material layer would finish earlier than the other part of the material layer, resulting in exposure of the gate insulating film 104. If the etching is continued to remove the remaining material layer, the exposed gate insulating film 104 and moreover the SOI layer would be etched. Thus, the structure of the SOI transistor can not be achieved. A method is desired with which the top and bottom surfaces of the material layer for the gate electrode can be formed to be planar so that deformation of the gate electrode is not caused in the etching process.